In U.S. Pat. No. 4,611,220, issued on Sept. 6, 1986, there is described an MOS transistor of the depletion mode type that features a small island of opposite conductivity type located in the normally conducting channel and maintained essentially at the potential of the gate electrode. The island serves as a sink to collect minority charge carriers that are attracted to the interface between the channel and the gate oxide when a voltage is applied to the gate electrode to deplete the channel of majority carries. Such minority charges, if not collected, make it difficult to turn off the transistor completely. Such a transistor has been described as a junction-metal-oxide-silicon field effect transistor, or more simply as a JMOS transistor.
In our application Ser. No. 077,742, filed July 27, 1987, and assigned to the same assignee as the instant application, now U.S. Pat. No. 4,746,960, there are described various improved forms of J-MOSFETs that include a two-dimensional array of cells sharing a common source electrode and a common drain electrode that are on opposite surfaces of a silicon chip. The chip includes an apertured buried oxide layer that divides it between a monocrystalline substrate portion and an epitaxial layer portion in which is formed a common channel layer divided into a plurality of segments, each controlled by a separate segment of a common gate electrode. Included in the common channel are a plurality of islands of opposite conductivity type that form back-to-back PN junctions for collection of charge carriers that tend to collect at the channel-gate oxide interface, as mentioned above. In such a structure, the back-to-back junctions are in the epitaxial silicon layer and so reduce the portion of the layer that can be used effectively as a channel for signal charge flow between source and drain.
It is desirable to form a J-MOSFET that uses its channel more efficiently.
Moreover, the inclusion of a buried oxide layer in the earlier form makes for relatively complex processing. It is therefore desirable in some instances to eliminate the need for such a buried oxide layer. To this end, the invention can be further extended to improve the recessed-gate JMOS transistor described in our earlier application Serial No. 923,583, filed Oct. 27, 1986, now U.S. Pat. No. 4,769,695, and thereby to provide an embodiment that does not include include a buried oxide layer.